Monday Q&A #11 (2023-05-15)

Answers to questions from last week's videos

May 15, 2023
∙ Paid

Each Monday I answer questions from the comments on the prior week’s videos. Transcripts are not available for Q&A videos due to length. I do produce closed captions for them, but Substack still has not enabled closed captions on videos :(

Questions addressed in this video:

  • [00:36] “While looking at the Godbolt disassemblies I noticed what appeared to be redundant mov instructions from registers to themselves (e.g. `mov rdi, rdi`). such mov instructions seem to be:

    - a way to clear the upper bits of a register

    - no-ops to align the addresses of instructions (because that matters, apparently)

    - no-ops as artifacts from a non-optimizing compiler

    It was also mentioned that they are an inefficient way of doing a no-op due to affecting the register's dependency chain.

    Is this information correct?”

  • [10:45] “You mentioned that we will rarely find instructions other than the ones we have seen (and SIMD) in compiler output. Yet there seem to be a lot more instructions than that in x64. Are those just for the benefit of people who program directly in assembly ? It seems like a huge effort to add all those instructions for such a small user base”

  • [18:12] “One question: you said they kept "ax" and such for backwards compatibility, does that mean that assembled programs for 8086 can be directly run on a x64 CPU?”

  • [20:44] “Little question about the emulator. When decoding the SEGMENT (override) instruction, what happens if the next instruction don't use it (for example when executing AAA) or the next instruction's operand segment cannot be overridden. Does the SEGMENT override resets? stays until used?”

  • [21:37] “I'm curious about register packing. Previously, in the 8086 architecture, the advantage of the first 8 registers had been that we could pack elements into two 8 bit values.

    I wonder if there is a similar way to pack two 32 bit or 4 16 bit values in a 64bit register with the ability to access those "High" ,"Medium" and "Low" bits (in 16/32 bit increments). Or should we just rely on SIMD to do that for us?”

  • [24:41] “Is a segfault something that is handled by the CPU? I.E. does a flag get set when we segfault sort of like how CMP operates on the FLAGS register, or is a segfault something handled by the OS somehow?”

  • [30:00] “I've seen a couple of other things not mentioned here that I had to google, most notably "rep stosq" and "cdqe" which I did not understand on my own.”

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