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Monday Q&A #4 (2023-03-06)

Answers to questions from last week's videos
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Each Monday I answer questions from the comments on the prior week’s videos. Transcripts are not available for Q&A videos due to length. I do produce closed captions for them, but Substack still has not enabled closed captions on videos :(

Questions addressed in this video:

  • [1:24] “Does the CPU use registers as a storage for instructions as well? If so, how some of the instructions fit into 16bit size register?”

  • [3:53] “This may just be a dumb question, but I wonder if there is a memory-to-memory operation as well? If yes, what does the REG component hold in that case? If not, why not? Is there some obvious problem with that operation?”

  • [6:54] “A question: I have seen several discussion on how to take advantage of data cache. I haven’t seen much on how to take advantage of instruction cache. Can you comment on this? How does one take advantage of instruction cache?”

  • [9:33] “Are modern CPUs such as Skylake or Zen still able to directly execute these 16 bit instructions? Or has the backward compatibility broken down at some point of the last 45 years?”

  • [12:05] “When debuggers show "disassembly", are they doing a similar thing of decoding/reverse-engineering a binary file of encoded assembly?”

  • [14:30] “Will we eventually include the CPU execution model in the multi-core context? I would LOVE to learn about how these things work at low level. For example, xchg for implementing lock, memory barrier, cache coherance etc. I have encountered these concepts before but never internalized them at a deep level.”

  • [16:53] “I can't find where the manual talks about the signed displacement? The only thing I found is the fact it sign-extends 8bit displacement to 16bit. Which means I just need to cast it to signed 8bit/16bit before printing it.”

  • [18:18] “With an underlying theme being that instruction decoding can be tricky and requires some twiddling, does the ‘promised’ performance in a CPU spec (i.e. the clock cycles, 4.7GHz for instance) exclude the overhead of decoding these instructions? Or is instruction decoding these days a more trivially solved problem and hence has negligible overhead?”

  • [24:02] “Can the assembly ever construct an immediate-to-register/memory with mod 11, or will that always be more compact as an Immediate-to-register? I noticed some solutions that didn't handle the first case, but I can't get nasm to generate it. I can manually create a test file with the bytes 0b11000110, 0b11000000, 0b00000001 (equivalent to mov al, byte 1, though if I give nasm that as input, it generates the equivalent of mov al, 1, which saves one byte).”

  • [26:35] “Something I've seen but is tricky to google for - is there a difference between eg. mov byte [address], imm or mov [address], byte imm?”

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Casey Muratori