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Q&A #52 (2024-04-29)

Answers to questions from the last Q&A thread.

In each Q&A video, I answer questions from the comments on the previous Q&A video, which can be from any part of the course.

Questions addressed in this video:

  • [00:02] “I would like to know your thoughts on one-shot projects vs projects that are delivered continuously across time (more service-like perhaps).”

  • [05:48] “Concerning the language problem with SIMD: Maybe you have already mentioned it during the course, but have you used ISPC already? This is a compiler from Intel that tries to address this problem. If yes, would you recommend it?”

  • [09:12] “A question on latency & bandwidth of different caches. In principle, even if L2 has higher latency than L1, it could "in theory" have the same bandwidth. I understand the reason why it is lower in practice is that there is not enough ‘workers’ available so that the chip can sustain say 2 mov issued by cycle (I don't know if there is a name for those ‘workers’, there are the equivalent of your ‘tax collectors’). Is there a way to measure how many such ‘workers’ there are for each cache level?”

  • [12:57] “Are you still using batch files to handle building so many targets at once? I don't have access to msvc but with gcc and clang the compile times with x86intrin.h included are quite high so I'm wondering if you split off multiple processes somehow and/or how you're handling it all.”

  • [14:50] “How do atomic instructions interact with the cache system? What does an instruction like ‘lock add QWORD PTR [rdi], 1’ (a 64 bit atomic increment) actually do? Does it lock other cores/threads out from just that memory location, or from the whole cache line? Does it evict the cache line from other cores' L1? Or can the behavior change from microarchitecture to microarchitecture?”

  • [31:42] “I noticed that in your implementation, you explicitly define backing type for enum. Can you explain if you did it on purpose (i.e. used 32-bit boolean and 32-bit enum). Is it related to cache lines somehow?”

  • [33:10] “You mentioned how you thought the way Rust and modern C++ do memory safety / allocation isn't useful to you because you use a software architecture that mitigates those problems. I would love some further elaboration on this.”

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