This is the third video in Part 1 of the Performance-Aware Programming series. Please see the Table of Contents to quickly navigate through the rest of the course as it is updated weekly. Homework data is available on the github. A lightly-edited transcript of the video appears below.
If you've done the homework so far, you probably “get” 8086 encoding now. Sure, there are a lot of instructions we haven’t decoded. But as voluminous as the instruction set is, it’s all built out of the same tricks. At the end of the day, you're looking at some bits and making decisions about whether to read another byte, while extracting useful portions of each byte to use for table lookups and values. There’s really not that much to any individual bit pattern, there’s just a lot of different patterns to handle.
But you now know the basic principles. And these same principles are still there in the modern x64 instruction set. Decoders for x64 machine code do the same sort of bit pattern analysis you’re doing to decode 8086 machine code. The patterns have evolved since the original, but now that you know how to decode 8086, you would instantly recognize x64 encodings.
What I'd like to do in this post is emphasize one last aspect of 8086 decoding. It's not only an interesting pattern in the way instructions are encoded, but it’s also a design decision intrinsic to all x86-derived processors that’s important to understand for performance analysis!
If you remember, one of the encodings for a mov instruction was some opcode bits, a d bit, a w bit, and then the “mod reg r/m” pattern:
