Computer, Enhance!

Branchless Absolute Value

Some operations are uniform enough that, even though we might ordinarily think of them as using a predicate, they can nonetheless be done by direct…

6 hrs ago

12

4

17:26

Three Steps from Scalar to SIMD

When we want to change the interior of a loop (with complex control flow) from processing one thing to processing several at a time, it's best to tackle…

Aug 3

49

2

1

20:13

June 2026

Q&A #86 (2026-06-10)

Answers to questions from the last Q&A thread.

Jun 10

49

30

1

51:12

May 2026

How to Use uops.info

Now that we've done our own microarchitecture investigations, it's time to get familiar with one of the best x64 microarchitecture data sites.

May 30

43

40:42

Q&A #85 (2026-05-26)

Answers to questions from the last Q&A thread.

May 27

50

10

1:22:46

April 2026

Block Interleaving

Breaking up dependency chains to better suit the processor's out-of-order scheduling gets most of the benefit of in-order interleaving without requiring…

Apr 28

50

1

35:48

Q&A #84 (2026-04-20)

Answers to questions from the last Q&A thread.

Apr 21

47

17

30:32

In-order Interleaving

By handing the CPU an instruction stream it can execute in order, we can exceed the limits we hit when we rely on its out-of-order execution…

Apr 16

59

38:11

March 2026

Q&A #83 (2026-03-11)

Answers to questions from the last Q&A thread.

Mar 12

56

19

1:16:33

Dependency Chain Stalls

The CPU's ability to extract parallelism has its limits.

Mar 4

77

5

1

29:55

January 2026

Q&A #82 (2026-01-27)

Answers to questions from the last Q&A thread.

Jan 27

66

25

4

48:27

December 2025

Dead Code Elimination Prevention Macros

Watch now (26 mins) | This is the eighth video in Part 5 of the Performance-Aware Programming series.

Dec 29, 2025

57

10

25:56